Over the last month I have been working on a five member team to construct an electronic locking system vault for my Digital Electronics class at school. We were given several requirement that we had to fulfill:
-Use a CPLD(Complex Programmable Logic Device) and program in VHDL
-Have a four digit LED display.
-Be able to enter a four digit code that will unlock the safe if it is correct.
-If the code is wrong sound a whooping-siren, false an alarm LED, and lock the keypad for 5 seconds.
-Have a button inside the vault that when pressed displays the current correct code and if held down a user can enter and reset to a new code of choice.
-Give a presentation and demonstration and turn in a report documenting the project
So, we got to work on building this device and spent ~100 man hours building, programming, assembling, and testing this device.
We needed to design a circuit to power the whooping/undulating siren and LED, a system clock, and control circuit to activate our solenoid lock.
An issue we had to work with in designing our circuit was the different power circuits needed. Our CPLD was designed to run at 3.3V while most Logic chips run at 5V. However, after testing we found most of the basic logic chips we were going to use, a 7-Segment LED decoder and NOT gate still ran reliably at 3.3V. Our 555 timers however did not, so we purchased 3.3V LVTTL(Low Voltage Transistor-Transistor Logic) chips to use and they worked well. However we still had to have a 5V power circuit isolated from the rest of the circuit to power our keypad which was a PS/2 computer keypad that was spec’d to run at 5V and in testing we could only get it to run reliably down to around 4.3-4.5V. That was all run from a single 9V battery running through two different transistor based voltage regulators. We then had 2 separate 9V batteries connected in a + voltage and a - voltage configuration to operate an Op-Amp that would boost a 3.3V signal output from the CPLD to 12V to power our solenoid lock and also provide nearly perfect isolation to prevent current surges from coursing back through our circuit and burning up our CPLD when the solenoid was turned off.
Our clock was going to be primarily running our display which would cycle through each of the four digits one at a time so we needed a clock that could display at a minimum 60Hz per digit, for a total of at least 240Hz. We ended up making a clock that ran at 400Hz because that assisted in the clock division inside the CPLD to produce a 5 second timer in code. To make the clock we used a LVTTL 555 timer with 2x 12K Ohm resistors and a .1 microF capacitor. The 555 timer does not put out a perfect square wave and so we were getting double triggers on each pulse, so we investigated using a schmitt trigger to clean it up, but we ended up just running it through a plain old NOT gate and that worked well.
An Oscilloscope Readout of Our Clock Signal
For the Siren circuit I used a modified version of a circuit I found on the internet. I changed some values, 47K to 10K, and removed a wire between pin 6 and 5 of the two timers. One of the timers produces a ~72Hz signal that makes the high pitched tone and the other produces a ~1Hz signal that causes the volume undulation of the other signal giving the siren sound. While it worked, it tended to be a rather finicky setup. It also interfered with our clock when it was on producing a low frequency beat on the clock signal and a high frequency interference on each square-wave pulse. We worked to remove this by investigating a ferrite bead, though we ended up being at too low of frequencies to use it, a voltage follower which removed the low frequency beat, and a capacitor to ground off the Vcc input line of the clock. This helped some, but not real well. Thankfully it ended up not mattering, as when the siren was on while the CPLD was counting the clock signals and dividing them down, in the scale of 5 seconds a few missed or double triggered pulses out of 400 didn’t make a noticeable difference. In the long run it would have been nice to just have used a dedicated external crystal oscillator for our clock so as to not have these problems.
Final Circuit Schematic
Our final circuit ended up being made on a solder less breadboard, but we had wanted to mill a PCB to solder all of the components on to for a far more finished look and to remove the worry of wires coming out at the last minute and not knowing where they need to go. One of our team members entered our circuit design into NI Ultiboard and was going to mill it. However, this to was foiled because of time constraints. We made some last minute hardware revisions, and more importantly we were not able to get our hands on a drill bit to finish our board in time to still be able to solder it up and have it ready to be presented since we were the second of six teams to present. Ideally, we would have had enough time to send our design off to have it laser etched which creates a far nicer board than a milling machine. Still, it was good experience to learn how this is done even if we only got it partly finished.
Our Essentially Completed Circuit Breadboard
For our keypad we used a PS/2 interface like from a computer keyboard. All the other teams used a matrix type keypad where the computer tested a matrix of connections to see where they were made and so what key is pressed. The keypad we used, while not looking as nice, was a little cheaper and used only two I/O pins on the CPLD rather than the 7-8 which initially we thought was going to be an issue. The PS/2 protocol uses a single data line and a single clock line to send synchronous data. The lines float high and when a key is pressed the clock is activated sending packets of 11 clock pulses with a data bit on each pulse. These 11 bits consist of a start bit(0), 8 data bits, an odd parity bit, and a stop bit(1). We hooked a keyboard up to a digital oscilloscope and looked at the data being sent to get a feel for what we needed to do and understand it better.
An Oscilloscope output of a packet being sent.
The protocol has certain make and break codes specified for each key. A make code is sent when the key is pressed and the break codes are sent when the key is released. Most keys have 1 make and 2 breaks for a total of 33 bits per key. However, some special keys, such as the keypad enter, use 2 makes and 3 breaks for 55 bits total which was a contingency we had to program for. The data is sent at ~12KHz. Once we had the protocol specified we just had a comparison table in the code to determine what button was pressed, and it turns out when dealing with only the keypad we only needed to inspect the first 4 data bits after the start bit to tell what key was being pressed which helped save on macrocells, program storage, in our code.
In terms of programming, which I was not in charge of, our two biggest challenges were learning VHDL and not being able to fit our I/O and logic on one chip. We continually ran out of macrocells, essentially the storage, and were unable to fit everything on one chip so we ended up using 2 CPLD chips and facilitating data communication between the two. This was a problem every team ran into. The other teams either used two CPLDs or just didn’t have full functionality with only one team being able to fit all essential functionality on one chip. A lab assistant at school who is quite proficient in VHDL also didn’t seem to think it was possible to fit everything onto one chip, of course this was the first semester this project has been done with this particular chip. In the end we ended up with ~450 lines of code, which with more time and VHDL experience probably could have been slimmed down a little.
Our box design we made out of wood instead of steel because of time constraints, and partly because of cost. Since it was wood we decided to make it kind of classy looking with a nice wood and a stained exterior. We did have a few hitches such as the hinges were on the outside of the door, unfortunately another side effect of time constraints and our mechanical engineer who was in charge of it was also involved in 3 other large projects in other classes over a similar time frame, but otherwise a very nice box.
Here is our completed vault and a video of it functioning. This was quite a large project for a sophomore level 3-hour class, but I guess that is Dr. Kim’s way and pleasantly when we presented our box and demonstrated it it worked quite well, something that seems to rarely happen on projects, praise the Lord.
The Electronics Compartment at the Top of the Vault
Hopps
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